/
usr
/
include
/
linux
/
/usr/include/linux
mkdir
upload
Name
Size
Mode
Actions
byteorder/
-
0755
rm
can/
-
0755
rm
dvb/
-
0755
rm
hdlc/
-
0755
rm
isdn/
-
0755
rm
netfilter/
-
0755
rm
netfilter_arp/
-
0755
rm
netfilter_bridge/
-
0755
rm
netfilter_ipv4/
-
0755
rm
netfilter_ipv6/
-
0755
rm
nfsd/
-
0755
rm
raid/
-
0755
rm
spi/
-
0755
rm
sunrpc/
-
0755
rm
tc_act/
-
0755
rm
tc_ematch/
-
0755
rm
usb/
-
0755
rm
wimax/
-
0755
rm
a.out.h
7319
0644
edit
dl
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acct.h
3490
0644
edit
dl
rm
adb.h
1077
0644
edit
dl
rm
adfs_fs.h
856
0644
edit
dl
rm
affs_hardblocks.h
1481
0644
edit
dl
rm
agpgart.h
3925
0644
edit
dl
rm
aio_abi.h
3112
0644
edit
dl
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apm_bios.h
3544
0644
edit
dl
rm
arcfb.h
150
0644
edit
dl
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atalk.h
927
0644
edit
dl
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atm.h
7806
0644
edit
dl
rm
atmapi.h
889
0644
edit
dl
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atmarp.h
1233
0644
edit
dl
rm
atmbr2684.h
3208
0644
edit
dl
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atmclip.h
513
0644
edit
dl
rm
atmdev.h
7593
0644
edit
dl
rm
atmioc.h
1583
0644
edit
dl
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atmlec.h
2561
0644
edit
dl
rm
atmmpc.h
4163
0644
edit
dl
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atmppp.h
576
0644
edit
dl
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atmsap.h
4907
0644
edit
dl
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atmsvc.h
1790
0644
edit
dl
rm
atm_eni.h
585
0644
edit
dl
rm
atm_he.h
343
0644
edit
dl
rm
atm_idt77105.h
892
0644
edit
dl
rm
atm_nicstar.h
1215
0644
edit
dl
rm
atm_tcp.h
1537
0644
edit
dl
rm
atm_zatm.h
1606
0644
edit
dl
rm
audit.h
15880
0644
edit
dl
rm
auto_fs.h
2346
0644
edit
dl
rm
auto_fs4.h
4131
0644
edit
dl
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auxvec.h
1384
0644
edit
dl
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ax25.h
2752
0644
edit
dl
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b1lli.h
1654
0644
edit
dl
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baycom.h
820
0644
edit
dl
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bfs_fs.h
1830
0644
edit
dl
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binfmts.h
565
0644
edit
dl
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blkpg.h
1598
0644
edit
dl
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blktrace_api.h
4473
0644
edit
dl
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blk_types.h
7106
0644
edit
dl
rm
bpqether.h
952
0644
edit
dl
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bsg.h
2385
0644
edit
dl
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can.h
3326
0644
edit
dl
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capability.h
10589
0644
edit
dl
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capi.h
3057
0644
edit
dl
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cciss_ioctl.h
5824
0644
edit
dl
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cdk.h
12770
0644
edit
dl
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cdrom.h
28129
0644
edit
dl
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cgroupstats.h
2155
0644
edit
dl
rm
chio.h
5280
0644
edit
dl
rm
cm4000_cs.h
1718
0644
edit
dl
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cn_proc.h
2715
0644
edit
dl
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coda.h
17487
0644
edit
dl
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coda_psdev.h
679
0644
edit
dl
rm
coff.h
12413
0644
edit
dl
rm
comstats.h
3120
0644
edit
dl
rm
connector.h
2129
0644
edit
dl
rm
const.h
682
0644
edit
dl
rm
cramfs_fs.h
2930
0644
edit
dl
rm
cuda.h
769
0644
edit
dl
rm
cyclades.h
17045
0644
edit
dl
rm
cycx_cfm.h
2926
0644
edit
dl
rm
dcbnl.h
22120
0644
edit
dl
rm
dccp.h
5800
0644
edit
dl
rm
dlm.h
2529
0644
edit
dl
rm
dlmconstants.h
5013
0644
edit
dl
rm
dlm_device.h
2480
0644
edit
dl
rm
dlm_netlink.h
1064
0644
edit
dl
rm
dlm_plock.h
806
0644
edit
dl
rm
dm-ioctl.h
10668
0644
edit
dl
rm
dm-log-userspace.h
15173
0644
edit
dl
rm
dn.h
4527
0644
edit
dl
rm
dqblk_xfs.h
6952
0644
edit
dl
rm
edd.h
5544
0644
edit
dl
rm
efs_fs_sb.h
2164
0644
edit
dl
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elf-em.h
1834
0644
edit
dl
rm
elf-fdpic.h
2557
0644
edit
dl
rm
elf.h
11236
0644
edit
dl
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elfcore.h
2932
0644
edit
dl
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errno.h
79
0644
edit
dl
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errqueue.h
443
0644
edit
dl
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ethtool.h
34166
0644
edit
dl
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eventpoll.h
1353
0644
edit
dl
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ext2_fs.h
18802
0644
edit
dl
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fadvise.h
855
0644
edit
dl
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falloc.h
293
0644
edit
dl
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fb.h
16016
0644
edit
dl
rm
fcntl.h
1607
0644
edit
dl
rm
fd.h
11563
0644
edit
dl
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fdreg.h
5355
0644
edit
dl
rm
fib_rules.h
1459
0644
edit
dl
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fiemap.h
2548
0644
edit
dl
rm
filter.h
3534
0644
edit
dl
rm
firewire-cdev.h
25053
0644
edit
dl
rm
firewire-constants.h
1975
0644
edit
dl
rm
flat.h
2085
0644
edit
dl
rm
fs.h
18910
0644
edit
dl
rm
fuse.h
11441
0644
edit
dl
rm
futex.h
4909
0644
edit
dl
rm
gameport.h
816
0644
edit
dl
rm
generic_serial.h
895
0644
edit
dl
rm
genetlink.h
1683
0644
edit
dl
rm
gen_stats.h
1304
0644
edit
dl
rm
gfs2_ondisk.h
11814
0644
edit
dl
rm
gigaset_dev.h
981
0644
edit
dl
rm
hayesesp.h
230
0644
edit
dl
rm
hdlc.h
574
0644
edit
dl
rm
hdlcdrv.h
2845
0644
edit
dl
rm
hdreg.h
22640
0644
edit
dl
rm
hid.h
1824
0644
edit
dl
rm
hiddev.h
6265
0644
edit
dl
rm
hidraw.h
1217
0644
edit
dl
rm
hpet.h
686
0644
edit
dl
rm
hysdn_if.h
1319
0644
edit
dl
rm
i2c-dev.h
2403
0644
edit
dl
rm
i2c.h
6631
0644
edit
dl
rm
i2o-dev.h
11488
0644
edit
dl
rm
i8k.h
1438
0644
edit
dl
rm
icmp.h
2892
0644
edit
dl
rm
icmpv6.h
3831
0644
edit
dl
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if.h
8673
0644
edit
dl
rm
if_addr.h
1456
0644
edit
dl
rm
if_addrlabel.h
658
0644
edit
dl
rm
if_arcnet.h
3718
0644
edit
dl
rm
if_arp.h
6109
0644
edit
dl
rm
if_bonding.h
4076
0644
edit
dl
rm
if_bridge.h
3810
0644
edit
dl
rm
if_cablemodem.h
910
0644
edit
dl
rm
if_ec.h
901
0644
edit
dl
rm
if_eql.h
1284
0644
edit
dl
rm
if_ether.h
6539
0644
edit
dl
rm
if_fc.h
1674
0644
edit
dl
rm
if_fddi.h
3700
0644
edit
dl
rm
if_frad.h
2940
0644
edit
dl
rm
if_hippi.h
4175
0644
edit
dl
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if_infiniband.h
1145
0644
edit
dl
rm
if_link.h
12078
0644
edit
dl
rm
if_ltalk.h
125
0644
edit
dl
rm
if_packet.h
3530
0644
edit
dl
rm
if_phonet.h
337
0644
edit
dl
rm
if_plip.h
596
0644
edit
dl
rm
if_ppp.h
6938
0644
edit
dl
rm
if_pppol2tp.h
1983
0644
edit
dl
rm
if_pppox.h
3772
0644
edit
dl
rm
if_slip.h
809
0644
edit
dl
rm
if_strip.h
700
0644
edit
dl
rm
if_tr.h
3199
0644
edit
dl
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if_tun.h
3014
0644
edit
dl
rm
if_tunnel.h
1459
0644
edit
dl
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if_vlan.h
1708
0644
edit
dl
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igmp.h
2928
0644
edit
dl
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in.h
9203
0644
edit
dl
rm
in6.h
7495
0644
edit
dl
rm
inet_diag.h
2453
0644
edit
dl
rm
inotify.h
2838
0644
edit
dl
rm
input.h
27594
0644
edit
dl
rm
in_route.h
873
0644
edit
dl
rm
ioctl.h
100
0644
edit
dl
rm
ip.h
3555
0644
edit
dl
rm
ip6_tunnel.h
1073
0644
edit
dl
rm
ipc.h
2038
0644
edit
dl
rm
ipmi.h
16543
0644
edit
dl
rm
ipmi_msgdefs.h
4477
0644
edit
dl
rm
ipsec.h
884
0644
edit
dl
rm
ipv6.h
2892
0644
edit
dl
rm
ipv6_route.h
1614
0644
edit
dl
rm
ipx.h
1824
0644
edit
dl
rm
ip_vs.h
12583
0644
edit
dl
rm
irda.h
7651
0644
edit
dl
rm
irqnr.h
93
0644
edit
dl
rm
isdn.h
5687
0644
edit
dl
rm
isdnif.h
2306
0644
edit
dl
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isdn_divertif.h
1038
0644
edit
dl
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isdn_ppp.h
1859
0644
edit
dl
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iso_fs.h
6439
0644
edit
dl
rm
ivtv.h
2726
0644
edit
dl
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ivtvfb.h
1143
0644
edit
dl
rm
ixjuser.h
25116
0644
edit
dl
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jffs2.h
6949
0644
edit
dl
rm
joystick.h
3587
0644
edit
dl
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kd.h
6169
0644
edit
dl
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kdev_t.h
298
0644
edit
dl
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kernel.h
2457
0644
edit
dl
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kernelcapi.h
959
0644
edit
dl
rm
keyboard.h
12695
0644
edit
dl
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keyctl.h
2984
0644
edit
dl
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kvm.h
20681
0644
edit
dl
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kvm_para.h
564
0644
edit
dl
rm
libc-compat.h
3540
0644
edit
dl
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limits.h
874
0644
edit
dl
rm
llc.h
2835
0644
edit
dl
rm
loop.h
2189
0644
edit
dl
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lp.h
3794
0644
edit
dl
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magic.h
2292
0644
edit
dl
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major.h
4655
0644
edit
dl
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map_to_7segment.h
7187
0644
edit
dl
rm
matroxfb.h
1429
0644
edit
dl
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mempolicy.h
2052
0644
edit
dl
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meye.h
2544
0644
edit
dl
rm
mii.h
7950
0644
edit
dl
rm
minix_fs.h
2059
0644
edit
dl
rm
mman.h
230
0644
edit
dl
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mmtimer.h
2054
0644
edit
dl
rm
mqueue.h
2055
0644
edit
dl
rm
mroute.h
3813
0644
edit
dl
rm
mroute6.h
3991
0644
edit
dl
rm
msdos_fs.h
5839
0644
edit
dl
rm
msg.h
2539
0644
edit
dl
rm
mtio.h
8080
0644
edit
dl
rm
nbd.h
1958
0644
edit
dl
rm
ncp.h
5055
0644
edit
dl
rm
ncp_fs.h
3354
0644
edit
dl
rm
ncp_mount.h
2112
0644
edit
dl
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ncp_no.h
651
0644
edit
dl
rm
neighbour.h
4060
0644
edit
dl
rm
net.h
2021
0644
edit
dl
rm
netdevice.h
1771
0644
edit
dl
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netfilter.h
1546
0644
edit
dl
rm
netfilter_arp.h
380
0644
edit
dl
rm
netfilter_bridge.h
735
0644
edit
dl
rm
netfilter_decnet.h
1872
0644
edit
dl
rm
netfilter_ipv4.h
2032
0644
edit
dl
rm
netfilter_ipv6.h
2050
0644
edit
dl
rm
netlink.h
4969
0644
edit
dl
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netrom.h
719
0644
edit
dl
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net_dropmon.h
1091
0644
edit
dl
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net_tstamp.h
3468
0644
edit
dl
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nfs.h
4351
0644
edit
dl
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nfs2.h
1405
0644
edit
dl
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nfs3.h
2207
0644
edit
dl
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nfs4.h
5763
0644
edit
dl
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nfs4_mount.h
1869
0644
edit
dl
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nfsacl.h
577
0644
edit
dl
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nfs_fs.h
1552
0644
edit
dl
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nfs_idmap.h
2238
0644
edit
dl
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nfs_mount.h
3200
0644
edit
dl
rm
nl80211.h
192354
0644
edit
dl
rm
nubus.h
8366
0644
edit
dl
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nvram.h
470
0644
edit
dl
rm
n_r3964.h
2349
0644
edit
dl
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oom.h
456
0644
edit
dl
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param.h
78
0644
edit
dl
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parport.h
3644
0644
edit
dl
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patchkey.h
831
0644
edit
dl
rm
pci.h
1485
0644
edit
dl
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pci_regs.h
37975
0644
edit
dl
rm
perf_event.h
21849
0644
edit
dl
rm
personality.h
1998
0644
edit
dl
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pfkeyv2.h
10147
0644
edit
dl
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pg.h
2282
0644
edit
dl
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phantom.h
1590
0644
edit
dl
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phonet.h
4349
0644
edit
dl
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pktcdvd.h
2623
0644
edit
dl
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pkt_cls.h
9293
0644
edit
dl
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pkt_sched.h
10887
0644
edit
dl
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pmu.h
5187
0644
edit
dl
rm
poll.h
96
0644
edit
dl
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posix_types.h
1270
0644
edit
dl
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ppdev.h
3147
0644
edit
dl
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ppp-comp.h
6516
0644
edit
dl
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ppp_defs.h
6461
0644
edit
dl
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pps.h
3939
0644
edit
dl
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prctl.h
4972
0644
edit
dl
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ptp_clock.h
3496
0644
edit
dl
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ptrace.h
2290
0644
edit
dl
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qnx4_fs.h
2265
0644
edit
dl
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qnxtypes.h
561
0644
edit
dl
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quota.h
5723
0644
edit
dl
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radeonfb.h
297
0644
edit
dl
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random.h
1085
0644
edit
dl
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raw.h
302
0644
edit
dl
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reboot.h
1280
0644
edit
dl
rm
reiserfs_fs.h
907
0644
edit
dl
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reiserfs_xattr.h
465
0644
edit
dl
rm
resource.h
2087
0644
edit
dl
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rfkill.h
3384
0644
edit
dl
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romfs_fs.h
1127
0644
edit
dl
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rose.h
2100
0644
edit
dl
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route.h
2269
0644
edit
dl
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rtc.h
3696
0644
edit
dl
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rtnetlink.h
15335
0644
edit
dl
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scc.h
4543
0644
edit
dl
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sched.h
2096
0644
edit
dl
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screen_info.h
2202
0644
edit
dl
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sdla.h
2837
0644
edit
dl
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selinux_netlink.h
1132
0644
edit
dl
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sem.h
3666
0644
edit
dl
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serial.h
6780
0644
edit
dl
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serial_core.h
4024
0644
edit
dl
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serial_reg.h
13245
0644
edit
dl
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serio.h
1688
0644
edit
dl
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shm.h
2187
0644
edit
dl
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signal.h
129
0644
edit
dl
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signalfd.h
1096
0644
edit
dl
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smb.h
1209
0644
edit
dl
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smbno.h
14520
0644
edit
dl
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smb_fs.h
535
0644
edit
dl
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smb_mount.h
468
0644
edit
dl
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snmp.h
11157
0644
edit
dl
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socket.h
738
0644
edit
dl
rm
sockios.h
5967
0644
edit
dl
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som.h
5480
0644
edit
dl
rm
sonet.h
2207
0644
edit
dl
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sonypi.h
5136
0644
edit
dl
rm
sound.h
1099
0644
edit
dl
rm
soundcard.h
46019
0644
edit
dl
rm
stat.h
1005
0644
edit
dl
rm
stddef.h
633
0644
edit
dl
rm
string.h
175
0644
edit
dl
rm
suspend_ioctls.h
1368
0644
edit
dl
rm
swab.h
6292
0644
edit
dl
rm
synclink.h
8695
0644
edit
dl
rm
sysctl.h
26495
0644
edit
dl
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taskstats.h
6947
0644
edit
dl
rm
tcp.h
5205
0644
edit
dl
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telephony.h
9051
0644
edit
dl
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termios.h
544
0644
edit
dl
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time.h
1736
0644
edit
dl
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times.h
215
0644
edit
dl
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timex.h
6221
0644
edit
dl
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tiocl.h
1666
0644
edit
dl
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tipc.h
5910
0644
edit
dl
rm
tipc_config.h
15370
0644
edit
dl
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toshiba.h
1284
0644
edit
dl
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tty.h
128
0644
edit
dl
rm
types.h
991
0644
edit
dl
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udf_fs_i.h
634
0644
edit
dl
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udp.h
1166
0644
edit
dl
rm
uinput.h
5125
0644
edit
dl
rm
uio.h
648
0644
edit
dl
rm
ultrasound.h
4499
0644
edit
dl
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un.h
203
0644
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Edit:
/usr/include/linux/serial_reg.h
(13245B)
/* * include/linux/serial_reg.h * * Copyright (C) 1992, 1994 by Theodore Ts'o. * * Redistribution of this file is permitted under the terms of the GNU * Public License (GPL) * * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). */ #ifndef _LINUX_SERIAL_REG_H #define _LINUX_SERIAL_REG_H /* * DLAB=0 */ #define UART_RX 0 /* In: Receive buffer */ #define UART_TX 0 /* Out: Transmit buffer */ #define UART_IER 1 /* Out: Interrupt Enable Register */ #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ /* * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1 */ #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ #define UART_IIR 2 /* In: Interrupt ID Register */ #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ #define UART_IIR_MSI 0x00 /* Modem status interrupt */ #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ #define UART_FCR 2 /* Out: FIFO Control Register */ #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ /* * Note: The FIFO trigger levels are chip specific: * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 * PC16550D: 1 4 8 14 xx xx xx xx * TI16C550A: 1 4 8 14 xx xx xx xx * TI16C550C: 1 4 8 14 xx xx xx xx * ST16C550: 1 4 8 14 xx xx xx xx * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 * NS16C552: 1 4 8 14 xx xx xx xx * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 * TI16C752: 8 16 56 60 8 16 32 56 */ #define UART_FCR_R_TRIG_00 0x00 #define UART_FCR_R_TRIG_01 0x40 #define UART_FCR_R_TRIG_10 0x80 #define UART_FCR_R_TRIG_11 0xc0 #define UART_FCR_T_TRIG_00 0x00 #define UART_FCR_T_TRIG_01 0x10 #define UART_FCR_T_TRIG_10 0x20 #define UART_FCR_T_TRIG_11 0x30 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ /* 16650 definitions */ #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ #define UART_LCR 3 /* Out: Line Control Register */ /* * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ #define UART_LCR_SBC 0x40 /* Set break control */ #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ #define UART_LCR_EPAR 0x10 /* Even parity select */ #define UART_LCR_PARITY 0x08 /* Parity Enable */ #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ #define UART_MCR 4 /* Out: Modem Control Register */ #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_OUT2 0x08 /* Out2 complement */ #define UART_MCR_OUT1 0x04 /* Out1 complement */ #define UART_MCR_RTS 0x02 /* RTS complement */ #define UART_MCR_DTR 0x01 /* DTR complement */ #define UART_LSR 5 /* In: Line Status Register */ #define UART_LSR_TEMT 0x40 /* Transmitter empty */ #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define UART_LSR_BI 0x10 /* Break interrupt indicator */ #define UART_LSR_FE 0x08 /* Frame error indicator */ #define UART_LSR_PE 0x04 /* Parity error indicator */ #define UART_LSR_OE 0x02 /* Overrun error indicator */ #define UART_LSR_DR 0x01 /* Receiver data ready */ #define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ #define UART_MSR 6 /* In: Modem Status Register */ #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ #define UART_MSR_RI 0x40 /* Ring Indicator */ #define UART_MSR_DSR 0x20 /* Data Set Ready */ #define UART_MSR_CTS 0x10 /* Clear to Send */ #define UART_MSR_DDCD 0x08 /* Delta DCD */ #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ #define UART_MSR_DDSR 0x02 /* Delta DSR */ #define UART_MSR_DCTS 0x01 /* Delta CTS */ #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ #define UART_SCR 7 /* I/O: Scratch Register */ /* * DLAB=1 */ #define UART_DLL 0 /* Out: Divisor Latch Low */ #define UART_DLM 1 /* Out: Divisor Latch High */ /* * LCR=0xBF (or DLAB=1 for 16C660) */ #define UART_EFR 2 /* I/O: Extended Features Register */ #define UART_EFR_CTS 0x80 /* CTS flow control */ #define UART_EFR_RTS 0x40 /* RTS flow control */ #define UART_EFR_SCD 0x20 /* Special character detect */ #define UART_EFR_ECB 0x10 /* Enhanced control bit */ /* * the low four bits control software flow control */ /* * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654 */ #define UART_XON1 4 /* I/O: Xon character 1 */ #define UART_XON2 5 /* I/O: Xon character 2 */ #define UART_XOFF1 6 /* I/O: Xoff character 1 */ #define UART_XOFF2 7 /* I/O: Xoff character 2 */ /* * EFR[4]=1 MCR[6]=1, TI16C752 */ #define UART_TI752_TCR 6 /* I/O: transmission control register */ #define UART_TI752_TLR 7 /* I/O: trigger level register */ /* * LCR=0xBF, XR16C85x */ #define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx * In: Fifo count * Out: Fifo custom trigger levels */ /* * These are the definitions for the Programmable Trigger Register */ #define UART_TRG_1 0x01 #define UART_TRG_4 0x04 #define UART_TRG_8 0x08 #define UART_TRG_16 0x10 #define UART_TRG_32 0x20 #define UART_TRG_64 0x40 #define UART_TRG_96 0x60 #define UART_TRG_120 0x78 #define UART_TRG_128 0x80 #define UART_FCTR 1 /* Feature Control Register */ #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ #define UART_FCTR_RTS_4DELAY 0x01 #define UART_FCTR_RTS_6DELAY 0x02 #define UART_FCTR_RTS_8DELAY 0x03 #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ /* * LCR=0xBF, FCTR[6]=1 */ #define UART_EMSR 7 /* Extended Mode Select Register */ #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ /* * The Intel XScale on-chip UARTs define these bits */ #define UART_IER_DMAE 0x80 /* DMA Requests Enable */ #define UART_IER_UUE 0x40 /* UART Unit Enable */ #define UART_IER_NRZE 0x20 /* NRZ coding Enable */ #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ #define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ #define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */ #define UART_FCR_PXAR8 0x40 /* receive FIFO treshold = 8 */ #define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */ #define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */ /* * These register definitions are for the 16C950 */ #define UART_ASR 0x01 /* Additional Status Register */ #define UART_RFL 0x03 /* Receiver FIFO level */ #define UART_TFL 0x04 /* Transmitter FIFO level */ #define UART_ICR 0x05 /* Index Control Register */ /* The 16950 ICR registers */ #define UART_ACR 0x00 /* Additional Control Register */ #define UART_CPR 0x01 /* Clock Prescalar Register */ #define UART_TCR 0x02 /* Times Clock Register */ #define UART_CKS 0x03 /* Clock Select Register */ #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ #define UART_FCL 0x06 /* Flow Control Level Lower */ #define UART_FCH 0x07 /* Flow Control Level Higher */ #define UART_ID1 0x08 /* ID #1 */ #define UART_ID2 0x09 /* ID #2 */ #define UART_ID3 0x0A /* ID #3 */ #define UART_REV 0x0B /* Revision */ #define UART_CSR 0x0C /* Channel Software Reset */ #define UART_NMR 0x0D /* Nine-bit Mode Register */ #define UART_CTR 0xFF /* * The 16C950 Additional Control Register */ #define UART_ACR_RXDIS 0x01 /* Receiver disable */ #define UART_ACR_TXDIS 0x02 /* Transmitter disable */ #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ #define UART_ACR_ICRRD 0x40 /* ICR Read enable */ #define UART_ACR_ASREN 0x80 /* Additional status enable */ /* * These definitions are for the RSA-DV II/S card, from * * Kiyokazu SUTO <suto@ks-and-ks.ne.jp> */ #define UART_RSA_BASE (-8) #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ #define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ #define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ #define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ #define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ #define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ #define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ #define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ #define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ #define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ #define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ #define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ #define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ #define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ #define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ #define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ /* * The RSA DSV/II board has two fixed clock frequencies. One is the * standard rate, and the other is 8 times faster. */ #define SERIAL_RSA_BAUD_BASE (921600) #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) /* * Extra serial register definitions for the internal UARTs * in TI OMAP processors. */ #define UART_OMAP_MDR1 0x08 /* Mode definition register */ #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ #define UART_OMAP_SCR 0x10 /* Supplementary control register */ #define UART_OMAP_SSR 0x11 /* Supplementary status register */ #define UART_OMAP_EBLR 0x12 /* BOF length register */ #define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ #define UART_OMAP_MVER 0x14 /* Module version register */ #define UART_OMAP_SYSC 0x15 /* System configuration register */ #define UART_OMAP_SYSS 0x16 /* System status register */ #define UART_OMAP_WER 0x17 /* Wake-up enable register */ #endif /* _LINUX_SERIAL_REG_H */
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cmd:
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